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L6245
5V HARD DISK DRIVE POWER COMBO
PRODUCT PREVIEW
General +5V OPERATION REGISTER BASED ARCHITECTURE MINIMUM EXTERNAL COMPONENTS SLEEP AND IDLE MODES FOR LOW POWER CONSUMPTION SELECTABLE GAINS FOR BOTH VCM AND SPINDLE Gm LOOP LINEAR CURRENT CONTROL LOOPS FOR BOTH VCM AND SPINDLE 8 BIT D/A FOR ACTUATOR DRIVER AND SPINDLE DRIVER VCM Driver CURRENT SENSE CONTROL (VOLTAGE PROPORTIONAL TO CURRENT) VOLTAGE SENSE CONTROL (VOLTAGE PROPORTIONAL TO THE VOLTAGE ACROSS THE VCM) TWO CURRENT RANGES FOR SEEKING AND TRACKING INTERNAL REGISTER FOR POWER AMP CONTROL LINES SPEED OUTPUT (VOLTAGE PROPORTIONAL TO BEMF) Spindle Driver BEMF PROCESSING FOR SENSORLESS MOTOR COMMUTATION PROGRAMMABLE COMMUTATION PHASE DELAY PROGRAMMABLE SLEW-RATE FOR REDUCED EMI 0.7 TYP. FOR ANY HALF BRIDGE CROSS CONDUCTION PROTECTION SYNTHESIZED HALL OUTPUT Other Functions POWER UP SEQUENCING POWER DOWN SEQUENCING LOW VOLTAGE SENSE ACTUATOR RETRACTION DYNAMIC BRAKE THERMAL SHUTDOWN
October 1992
MULTIPOWER BCD TECHNOLOGY
PQFP64 ORDERING NUMBER: L6245
DESCRIPTION The L6245 contains in a single chip all the functions to operate a sensorless brushless (DC) motor and a voice coil motor, suitable for hard disk drive applications. The device is configured to interface directly to an 8 bit parallel microprocessor bus, and has a register based architecture to reduce number of interconnection lines. All the positioning loop for sensorless spindle is integrated, including BEMF sensing, digital masking, digital delay and sequencing. All timing function are performed digitally, thus no external filtering components are required. The VCM driver is a transconductance amplifier, able to provide 2 different current ranges, suitable for seeking or tracking of the head actuator. When a low voltage is detected, a monitor, in sequence, resets the internal registers, puts in tristate the spindle powers, retracts the actuator, and applies the dynamic brake of the spindle. The L6245 is realized in Multipower-BCD 2 technology, which combine isolate DMOS power transistors with CMOS and Bipolar circuits in the same monolithic layer, and is assembled in a 64pin PQFP.
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This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L6245
BLOCK DIAGRAM
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L6245
PIN CONNECTION (Top view)
ABSOLUTE MAXIMUM RATINGS
Symbol Vds sus VP; Vcc Vi Vcp Ip IO Ptot Tstg, Tj Supply Voltage Logic input Voltage Charge Pump Input Voltage Sink-Source Peak Output Current Sink-Source DC Output Current Total Power Dissipation (Tamb = 60C) Storage and Junction Temperature Parameter Peak Output Sustaining Voltage Power (VP) Logic (VCC) Value 14 8 6 0 to 6 18 1.5 1 1 -40 to 150 Unit V V V V V A A W C
THERMAL DATA
Symbol R thj-amb Parameter Thermal Resistance Junction-ambient (*) max. Value 90 Unit C/W
(*) Mounted on a typical PCB layout (see Fig. 7)
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L6245
PIN DESCRIPTION [Pin Types: I = Input, O = Output, P = Power, A = Analog (passive)] Power
Pin Number 12, 17 24, 3 7, 42, 64 10 59 Pin Name VPOWER VDIG VCC GND VREF POR Pin Type P Description Positive supply, nominally 5V.
P I 0
Ground. All analog signals are referenced to this voltage, nominally 2V. POWER ON RESET - Goes low when the supply voltage is below the VOLTAGE GOOD threshold. POR is an open collector output with an internal 20k pull-up. POR DELAY. An external parallel RC network from this pin to ground sets the time the POR signal stays active after voltage good. An external capacitor from this pin to ground provides filtering for the VCC sense input of the POR circuit. Charge pump capacitor Charge pump inductor
61 62 5 6
POR_DLY POR_FILT CPC CPL
A A A A
Microprocessor Interface
Pin Number 25 26 27 28 29 30 31 32 38 39 35 41 33 34 35 37 43 Pin Name D7 D6 D5 D4 D3 D2 D1 D0 RD WR MC_CS SYSCLK A0 A1 A2 AS MC_ERR Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I O Description An 8-bit bidirectional data bus which is connected to the internal registers.
READ A low level on this pin allows the bus to be driven by the IC. A low level on WRITE allows the IC to read data from the system bus. CHIP SELECT A low level on this pin selects the IC for bus transactions. Microprocessor clock used for internal timing. The lowest three bits of the system address bus; used to address internal registers ADDRESS STROBE The address appearing on A [0:2] is latched on the falling edge of the AS pulse. A maskable interrupt signal which is asserted low when an error flag in the Status Register is set. The output is open-drain with an internal 20K pull-up. An open drain, active low signal used for asynchronous bus transactions.
40
DTACK
O
Brushless, Sensorless Motor Driver and 8 bit D/A
Pin Number 47 48 45 53 57 60 4/15 Pin Name SPIN_DAC SPIN_CMD COIL_CT COIL_U COIL_V COIL_W Pin Type O I I O Description The output of an 8 bit D/A used for the command to the spindle driver. The input to the spindle driver transconductance amplifier. The center tap of the motor is connected to this pin. The motor coils are driven by these outputs. Back EMF is also sensed at these pins.
L6245
PIN DESCRIPTION (continued)
Pin Number 44 49, 50, 58 46 56 51 Pin Name SYNTH_HALL SPIN SENSE 1,2,3 PWM_OFFT SLEW S_COMP Pin Type O A A A A Description A TTL compatible signal that emulates one of the Hall signals. SYNTH_HALL is an open drain output with an internal 20K pull-up. The current sensing resistors is connected from these pins to ground. A parallel R-C from this pin to ground sets the PWM mode OFF time. A resistor from this pin to ground sets the slew rate of the driver. An R-C network from this pin to GND sets the spin driver compensation.
VCM Driver and 8 bit D/A
Pin Number 8 9 21 14 23 13 15 20 19 16 18 22 Pin Name VCM_DAC VCM_CMD VCM_COMP VCM_RS1 VCM_RS2 VCM+ VCMOV_VOLT OV_CUR OV_SUM- OV_SUM_OUT ISENSE Pin Type O I A A A O O O O I O O Description The output of an 8 bit D/A used to command the VCM driver. VCM driver input command which is relative to VREF. An R-C network from this pin to ground compensates the VCM driver. The high gain current sense resistor is attached from this pin to ground. The low gain current sense resistor is connected from this pin to VCM_RS1 One end of the load is attached to this pin (Positive). The other end of the load is attached to this pin (Negative). A voltage which is proportional to the voltage across the load, referenced to VREF. A voltage which is proportional to the current through the load, referenced to VREF. Over-velocity summing op-amp inverting input. Over-velocity summing op-amp output. A voltage which is proportional to the current through the VCM load as sensed by the sense resistor. This signal is enabled by setting bit 2 in the VCM Control Register. The 8 bit input to the VCM D/A is updated on the rising edge of VCM_STRB.
54
VCM_STRB
I
Solenoid Pre-drivers and Power Down Sequencing
Pin Number 11,55, 63 2 Pin Name V_RECIR Pin Type P Description Under normal conditions, power is supplied to various blocks via the V_RECIR pin. When external power is removed, energy stored in the rotating spindle is converted to a voltage which supplies the park circuit. When a logic one is written to bit 3 of the VCM Control Register, current is sourced from the LOAD_SOL pin. Otherwise, the pin is high impedance. When a logic one is written to bit 4 of the VCM Control Register, current is sourced from the UNLOAD_SOL pin. Otherwise, the pin is high impedance. When power is removed, the charge stored on this capacitor keeps selected blocks alive long enough to effect an orderly power down. An external parallel RC network from this point to ground delays activation of the dynamic brake after power is removed.
LOAD_SOL
O
1
UNLOAD_SOL
O
4 52
PD_SEQ_CAP BRK_DLY
A A
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L6245
ELECTRICAL CHARACTERISTICS (VS = 5V, Tj = 25C; unless otherwise specified) Power Supply Characteristics
Symbol VS ID-READY ID_IDLE ID_SLEEP Parameter Supply Voltage Quiescent Current Dissipation Test Condition VS = VP = VCC No load attached VCM and Spin drivers enab. VCM driver disabled Spin driver enabled VCM and Spin drivers disabled Min. 4.5 Typ. Max. 5.5 25 20 4 Units V mA mA mA
VCM Driver (Notes 1, 2)
IOS IOT R DS(on) R DS(on) R DS(on) VF Vjump VDB VCMOS Maximum Load Current (Seeking) Maximum Load Current (Traking) Source & Sink Out ON Resistance Sink Out On Resistance Sink Out On Resistance Body Diode Forward Drop Jump Discontinuity (**) Deadband Discontinuity (*) Offset (***) Output Devices A, B, E, F (Fig. 1) Output Devices C, D (Fig. 1) Output Devices A, B, E, F Tj = 125C (Fig. 1) Output Devices C, D Tj = 125C (Fig. 1) Parking Device Tj = 125C I = 0.3A R sense = 2.01 R sense = 2.01 R sense = 2.01 0.3 0.1 1 2.4 12 1.5 30 6 40 A A V mV mV mV
(*) The range of input voltages applied to the VCM_CMD pin (with respect to VREF) for which only negligible current is present in the load. This deadband voltage (VDB) can be expressed either in mV or in LSBs, where one LSB is equal to 11.7mV. (**) A condition in which the transfer characteristic (i.e., load current vs. VCM_CMD-VREF) exhibits a slope which is significantly grater than the desired value. The range of currents for which this condition exists is termed IJUMP. This current is referred o the VCM_CMD input according to the following equation: VJUMP = IJUMP x 3 x RSENSE In this document, RSENSE is assumed to be 2.01. VJUMP can be expressed either in mV or in LSBs, where one LSB is equal to 11.7mV. (***) The value of VCM_CMD (with respect to VREF) for which the load current is zero. In parts which exihibit a DEADBAND dicontinuity, the offset is defined to be at the midpoint of the deadband region. RSENSE is assumed to br 2.01.
VCM Current sense amplifier (ISENSE)
Voff G PSRR BW VOR Output Offset Voltage Closed Loop Voltage Gain Power Supply Rejection Ratio Banwwidth Output Range VCC = 4.5V (note 4) VCM_RS2 Shorted to GND O/S is V(Isense) - Vref 3V/V nominal at DC -50 2.85 50 200 -0.2 3.5 50 3.15 mV V/V dB KHz V
VCM Full wave rectifying amplifier
IB Iimp G PSRR GBW CMR VOR Input Bias Current Input Impedance Closed Loop Gain Power Supply Rejection Ratio Unity Gain Bandwidth Input Common Mode Range Output Range VCM_CMD pin at DC VCM_CMD = Vref Impedance seen at VCM_CMD wrt V ref 5 0.320 50 200 0.3 0 3.7 1 0.347 2 A K V/V dB KHz V V
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ELECTRICAL CHARACTERISTICS (Continued) VCM DAC (Notes 5, 6)
Symbol Res N.L. I.N.L. CT ZO FSTC VOH VOL VZSO Parameter Resolution Differential Nonlinearity Integral Nonlinearity Conversion Time Output Z Full Scale Temp. Coeff. High Output Voltage Low Output Voltage Zero Scale Offset Relative to Vref Input Code = 7Fh Relative to Vref Input Code = 80h Relative to Vref Input Code = 00 1.46 -1.53 From 50% point of WR falling to 1% settling Test Condition Min. 8 0.5 0.5 2 100 200 1.52 -1.47 10 Typ. Max. Units bit LSB LSB s ppm/C V V mV
Over velocity detector, coil voltage sense amplifier
Symbol VO Parameter Output Offset Voltage Test Condition VCM+ = VCM-, within input common mode range. Measure wrt to Vref (Note 3) Av = 0.25V/V nominal at DC Above and below these values the op amp will be in saturation and will not invert sign. 0.242 50 200 0 VPOWER Min. -50 Typ. Max. +50 Units mV
IBC G PSRR BW CMR
Input Bias Current Closed Loop Voltage Gain Power Supply Rejection Ratio Bandwidth Input Common Mode Range
10 0.258
A V/V dB KHz V
VDR VOR IO
Input Differential Range Output Range Output Current
0 0.3 ae400
VPOWER 3.5
V V A
Over velocity detector, coil current sense amplifier
Symbol VO Parameter Output Offset Voltage Test Condition VCM_RS1 shorted to GND for: (a) VCM_CMD < Vref and b) VCM_CMD > Vref. Measure wrt Vref Av = 2.5V/V nominal at DC Min. -50 Typ. Max. +50 Units mV
G PSRR Bw CMR VR IO
Closed Loop Voltage Gain Power Supply Rejection Ratio Bandwidth Input Common Mode Range Output Range Output Current
2.425 50 200 -0.1 0.5 +400
2.575
V/V dB KHz
2 3.5
V V mA
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L6245
ELECTRICAL CHARACTERISTICS (Continued) Over velocity detector, summing amplifier
Symbol VO IBC G PSRR GBW VR IO Parameter Input Offset Voltage Input Bias Current Open Loop Gain Power Supply Rejection Ratio Unity Gain Bandwidth Output Range Output Current at DC 60 50 200 0.5 +400 3.5 Test Condition Min. Typ. Max. 10 1 Units mV A dB dB KHz V A
Over velocity detector, window comparator
Symbol tS VTL VTH Parameter Switching Time Low Threshold High Threshold Relative to Vref Relative to Vref -1.32 1.18 Test Condition Min. Typ. Max. 50 -1.18 1.32 Units s V V
Solenoid pre-driver (Note 7)
Symbol IOH Parameter Output Current Test Condition VOH = 1.5V, VCC = 4.4V Min. 10 Typ. Max. Units mA
Three phase sensorless motor driver
Symbol IO R DS(on) dV/dt VF Parameter Max. Load Current Out On Resistance Slew Rate Body Diode Forward Drop I = 0.5A Tj = 125C 0.05 1.2 Test Condition Min. Typ. Max. 0.5 0.75 Units A V/s V
Motor Current Sense Amplifier
Symbol IBC G PSRR BW IO Parameter Input Bias Current Closed Loop Voltage Gain Power Supply Rejection Rate Bandwidth Output Range Low Gain mode High Gain mode at DC 19.4 4.85 50 200 0 3.2 Test Condition Min. Typ. Max. 1 20.6 5.15 Units A V/V V/V dB KHz V
Spin DAC (Notes 8, 9)
Symbol Res NL INL CT Zo FSTC VOH VOL Parameter Resolution Differential Nonlinearity Integral Nonlinearity Conversion Time Output Z Full Scale Temp. Coeff. High Output Voltage Low Output Voltage Unloaded 2.85 0 From 50% point of -WR falling to 1% settling Test Condition Min. 8 0.5 0.5 5 14 200 3.15 20 Typ. Max. Units bit LSB LSB s K ppm/C V mV
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L6245
ELECTRICAL CHARACTERISTICS (Continued) Step-up converter
Symbol VSU Parameter Step-up Voltage Test Condition Relative to VCC Min. 7 Typ. Max. 11 Units V
Microprocessor interface (Note 10)
Symbol VIH VIL VOH VOL1 VOL2 IIN1 IIN2 Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Low Level Output Voltage Input Leakage Current Input Leakage Current VCC = 5V, IOH = 400A -MCERR, -POR, -DTACK IOL = 4mA SYNT_ALL IOL = 0.5mA -RD, -WR, AS, -MC_CS, SYSCLK, A [0:2] D [0:7] 4.4 0.4 0.4 1 10 Test Condition Min. 3 0.8 Typ. Max. Units V V V V V A A
Microprocessor interface timing
Trddh Trddt Twrdt Read Data Hold -RD High to -DTACK high -WR High to -DTACK High 5 40 40 40 ns ns ns
Power on reset
VCCHL VCCHL TPLH RT VCC Good, HL VCC Good, LH Rise Time Response Time VCC falling VCC rising C Load = 100pF 4.2 4.26 4.4 4.5 200 50 V V ns s
Notes: 1) The minimum voltage available from the brushless DC motor after power has been removed is 2.7V 2) The voltage available for actuator etraction shall be greater than 0.7V. 3) Sum of Ibias+(Vref/internal resistor + power leakage). 4) Minimum output voltage is set to Vref by a resistor network. 5) The VCM DAC shall be monotonic over its full range. 6) The coding of the digital input shall be 2's complement. 7) The voltage available for solenoid operation shall be greater than 1.9V. 8) The Spin DAC shall be monotonic over its full range. 9) The coding of the digital input shall be uniplar (unsigned binary). 10) SYNTH_HALL, MC_ERR, DTACK and POR shall have open drain (collector) outputs and internal pull-up resistors. The minimum value of these pull-up resistors shall be 20K..
FUNCTIONAL DESCRIPTION Inside the system is the sensorless Spindle driver (Spin), the Voice Coil Motor driver (VCM), the Head load/unload predrivers, power sequencing, actuator over-velocity detection, actuator retraction and dynamic braking. The architecture of the system is configured to interface directly to an 8 bit, parallel, microprocessor bus. During the application of power to the system (power-on), the output drivers are held in a disabled state until the applied voltage reaches the Voltage Good Threshold (VGT). During this period of time the output drivers are disabled, the internal register are set to predetermined states, and the Power On
Reset (POR) signal is held low. The POR signal is held low from the time the applied voltage reaches 0.7V and the VGT. The POR delay is programmable changing the value of a capacitor. The VCM driver is driven via a D/A and it can be enabled through the VCM driver register. The VCM driver has a gain capability too. This function is to be accomplished by switching the sense resistor used such that the current sensing feedback in the VCM driver has more information and therefore results in lower deadband, offset current, and gain error. An actuator over velocity sensing circuit is incorporated in the system, which is accomplished by measuring BEMF voltage and comparing to a threshold.
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L6245
The head load /unload mechanisms are just buffers for driving external power transistors. Controlled internally by Bit 3 and Bit 4 of the VCM Driver Register, each output has a current surcing capability of 10mA. The Sensorless Spindle Driver function can be accessed from the microprocessor over the data bus to the Spin Register and Spin D/A. The Spin D/A is in Binary format. The operation of the Spindle system is controlled entirely by the microprocessor from start-up to speed regulaton. The spin system is accessible by selecting the Spin Control Register with the address 011 on the 3 bit address bus and has the following functions: 1)Enable (Bit 0): high to enable the spin system, while a low asserts braking of the spindle motor (if VCR enable is low.) 2)Sense amplifier gain (Bit 1): high implies high current mode which is equivalent to low sense amp gain, while a low selects low current mode or high sense amp gain. 3)Unipolar/Bipolar (Bit 2): High selects the Unipolar driving mode. 4)Run/Search Mode (Bit 3): high selects the run mode whereby the Hall synthesizer output gives speed information while a low asserts the search mode whereby the sequencer is under P control (stepper function). 5)Reset State (Bit 4): a low level resets the commutation state sequencer. 6)Incremental state (Bit 5): toggling of the bit increments the sequencer to drive the output stage when search mode is selected. 7)Linear/PWM (Bit 6): high selects linear mode of driving for current (speed) regulation while a low sets to PWM mode used during start-up. Start-up current limiting is accomplished by the output of the microprocessor commanded D/A value. Jammed or stuck rotor detection is also done as part of the microprocessor algorithm. Integrated diode are present in the power bridge for BEMF rectification. This rectified voltage is used to retract the actuator and unload or latch the head assembly. A conventional Bandgap is used to generate internal biasing for the device as well as the reference voltage for the D/A converters. A Step-up Converter is used to generate a 15V internal supply to drive the upper DMOSs and a regulated 11.6V internal supply to power internal circuits which have voltage head room problem, as well as to drive the lower DMOSs. A Low Voltage Detector (LVD) is incorporated to sense a severely low value of applied voltage so as to shunt-down the VCM and Spindle drivers. The LVD is activated when the applied voltage drops below 4.3V (+/-0.1V). When a voltage drop is sensed, the LVD: 1. asserts POR, which resets the internal register ; 2. retracts the actuator ; 3. applies the dynamic brake. When a severe low value of applied voltage is sensed, the motor control system goes into reset mode and also asserts the POR line to reset other circuits. The sub-circuit which get affected by the reset mode in the motor control system are the Spin Control Register, the VCM Driver Register, the Spindle D/A and the VCM D/A. This effectively disables the spin driver, VCM driver, head load/unload driver and initializes the D/A's at zero output command value. An Over Velocity Detector circuit is integrated to sense when head arms are moving at a speed which could cause a damaging condition. When an over velocity condition is detected sensing the actuator BEMF, the actuator driver is shut off and held off until the microprocessor has detected this condition and then resets the error and retries the access. The microprocessor has the possibility to put the device in sleep mode, which is asserted when both the VCM and Spindle drivers are disabled through the internal registers (Enable VCM and Enable Spindle). Under this condition, only the POR circuit is kept "alive", thus power consumption is kept at minimal. Before sleep mode is activated, the microprocessor must move the actuator to the unload zone, unload the recording heads, and apply dynamic braking. All bits of all the registers are readable by the microprocessor interface. Also there are certain bits of the internal registers which are writable as defined in the Register Definition Tables (Tables 1 7). An internal register monitors the internal work of the system and latches certain error condition that are detected.
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L6245
REGISTER DEFINITION and 3bit Address Code Table 1: Status Register (A.C. 001)
Bit 7 6 5 4 3 2 1 0 Name NC NC NC NC REVERSE SPIN OVER TEMP. SPIN SENSE OVER VEL SET POR Initial Value
Table 5: Spin D/A Register (A.C. 101)
Bit 7 6 5 4 3 2 1 0 Name Most Significant Bit POR Initial Value 0 0 0 0 0 0 0 0
1 1 0 1
Least Significant Bit
Table 6: Interrupt Mask Register (A.C. 110) Table 2: VCM Driver Register (A.C. 010)
Bit Bit 7 6 5 4 3 2 1 0 Name NC NC NC UNLOAD HD LOAD HD ENABLE ISENSE HIGH GAIN VCM ENABLE VCM POR Initial Value 7 6 5 4 3 2 1 0 Name NC NC NC NC NC MASK REV Spin MASK OVER TEMP ERROR MASK OVER VEL ERROR POR Initial Value
0 0 0 0 0
0 0 0
Table 7: Phase Delay Register (A.C. 111) Table 3: Spin Control Register (A.C. 011)
Bit Bit 7 6 5 4 3 2 1 0 Name NC LINEAR/PWM INCREMENT STATE RESET STATE RUN/SEARCH UNI/BI HIGH GAIN SPIN ENABLE Spin POR Initial Value 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Name NC NC NC NC Most Significant Bit Least Significant Bit POR Initial Value
0 0 0 0
Table 4: VCM D/A Register (A.C. 100)
Bit 7 6 5 4 3 2 1 0 Name Most Significant Bit POR Initial Value 0 0 0 0 0 0 0 0
Least Significant Bit
SYSTEM BUS DESCRIPTION The system bus is designed as a data acknowledge handshanking bus. At the beginning of the bus cycle the address and chip select are decoded transparently and qualified with read or write going low. On a read operation, data must not be driven for 5nsec after read goes low to allow the bus to clear. Once data is driven, data acknowledge is driven low to notify the processor that data is on the bus and ready to be read. The processor reads the data and responds by raising read. This is an indication that the processor has compleated the read and cycle is complete. Data acknowledge and data must go to high impedence within 20ns to clear the bus for the next
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L6245
cycle. On a write operation, following write going low and whatever setup time required to latch data, data acknwledge is driven low. This notifies the processor that the cycle can end. This processor responds by raising write, indicating the end of the cycle. Data acknowledge must go to high impedance within 20nsec to clear the bus for the next cycle. This handshaking design allows a peripheral to control the length of the bus cycle. The peripheral Figure 1: System Bus Timing (see Table 8) can take as much time as it needs to drive data onto the bus, then drive DTACK low. Likewise, the peripheral can wait as long as it needs to set up data and latch it (or set up data if WR is used to latch), then drive DTACK low. However, performance is an issue, so even though this control has been given to the peripheral, it must not be abused. All delays are minimized to assure optimum system speed, infact the bus can be driven synchronously (E.G. has regarding DTACK) when procesor clocks below 12MHz are used.
Table 8: System Bus Timing
Symbol TAS TCS TASW TASRD TRDDV TRDDH TRDCS TDVDT TDTRD TRDDT TASWR TDVWR TWRDTL TDTWR TWRCS TWRDT TWRDH 12/15 Description Address Setup Time (non MUX bus; (MUX bus) System Select to Address Strobe Address Strobe Width Address Strobe to RD RD to Data Driven Read Data Hold RD High to CS High Data Valid to DTACK DTACK to RD High RD High to DTACH High Address Strobe to WR Write Data Valid to WR WR to DTACK DTACK to WR High WR High to CS High WR High to DTACK High Write Data Hold
L6245
THERMAL CHARACTERISTICS On the application, the L6245 must be soldered on a PCB system. The Traks Area, depending on the lenght and the width of each track, must be between 2 to 10 square mm. An area of 10 mm2 can give a typ. Thermal Resistance Junction-toAmbient value of 85C/W (See Fig. 2): this value refer3 to a Total Power Dissipated Power of 1W. Figure 2: Typical Rth j-amb vs. Tracks Area on PCB Fig. 9 shows the increase of the Rth j-amb when the Dissipated Power decreases. Practically, very useful information is the change of the thermal resistance (Thermal Impedance) versus a single pulse of power width or versus the time the dissipation begins. Fig. 4 shows this Thermal Impedance trend. Figure 3: Typical Junction-to-Ambient Thermal Resistance vs. Total Dissipated Power. (L6245 mounted on a typical PCB)
Figure 4: Typical Transient Thermal Impedance vs. Time or Pulse Width. (L6245 mounted on a typical PCB)
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L6245
PQFP64 PACKAGE MECHANICAL DATA
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 K L L1 0.65 0.80 1.60 16.95 13.90 0.25 2.55 0.30 0.13 16.95 13.90 17.20 14.00 12.00 0.80 17.20 14.00 12.00 0(min.), 7(max.) 0.95 0.026 0.0315 0.063 0.0374 17.45 14.10 0.667 0.547 2.80 3.05 0.45 0.23 17.45 14.10 mm TYP. MAX. 3.40 0.010 0.100 0.0118 0.005 0.667 0.547 0.677 0.551 0.472 0.0315 0.677 0.551 0.472 0.687 0.555 0.110 0.120 0.0177 0.009 0.687 0.555 MIN. inch TYP. MAX. 0.134
D D1 A D3 A1 48 49 33 32
0.10mm Seating Plane
A2
B
E3
E1
64 1 e 16
17 C
L1
E
L
K
PQFP64
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B
L6245
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.
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